1. Technical Field
The present subject matter relates to configuration of an integrated circuit, and more specifically, to self-healing and reconfiguration of an integrated circuit without an external service processor.
2. Description of Related Art
Level Sensitive Scan Design (LSSD) methodology allows latches of an integrated circuit to be accessible via scanrings. By shifting these scanrings, the chip designers, test lab engineers, etc. are able to read the content of individual latches in the chip to determine the chip status and to change the contents of a latch to modify the chip behavior. This methodology allows the designer to diagnose the chip, reconfigure it by enabling or disabling certain functional units or perform repair actions by correcting invalid latch contents. The scanring shift operations are performed in a clock stop state, i.e. clocks in the chip have to be stopped to freeze the chip to a stable state. In the some chip designs the scanrings are grouped into scan regions, or clock regions. Each clock region has individual clock gating, which allows the processing clock for one region to be stopped, while other regions continue to be operational.
Scanring reads and writes have been performed by an out-of-band processor, or service processor, in the past, using a special debug interface like JTAG to read out a scanring, modify it, and write the modified data back to the scanring of the chip. In order to perform the scanring operations from an external processor, an access path from the debug interface up to the unit to be modified is used as well as the pervasive unit, which is responsible for servicing the debug interface and performing the scanring operations.